Device operation clock and data conversion


Updated By : November 14, 2019 6:23:14 PM JST

Device operation clock and data conversion

Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (refer toData Validity timing diagram).

Data changes during SCL high periods will indicate a startor stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start conditionwhich must precede any other command (refer to Start and Stop Definition timingdiagram).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby powermode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from theEEPROM in 8-bit words.

The EEPROM sends a zero to acknowledge that it hasreceived each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C01A/02/04/08/16 features a low-power standby modewhich is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and thecompletion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:1. Clock up to 9 cycles.2. Look for SDA high in each cycle while SCL is high.3. Create a start condition.

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Author : idyllicvision | 11/14/19 6:23 PM | Public
Tags : Lifestyle
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